If DMA transaction is ongoing when RX is enabled, this can lead
to stuck communication between DMA and SSP (DMA service request
not seen by the DMA).

To avoid this, flush the RX fifo before enabling SSP RX.

Link: thesofproject#7548
Suggested-by: Peter Ujfalusi <[email protected]>
Signed-off-by: Kai Vehmanen <[email protected]>
(cherry picked from commit 4a4d8d2)
(cherry picked from commit 2c3f370)

The receive FIFO needs to be drained in a different way depending when it
is done.
- before start
If the RX FIFO is in overflow state then we must read all the entries out
to empty it (it was after all full).

- before stop
The DMA might be already running to read out data. Check the FIFO level
change in one sample time which gives us the needed information to decide
to wait for another loop for the DMA burst to finish, wait for the DMA to
start it's burst (DMA request was asserted) or drain the FIFO directly.

No need to drain the RX fifo at probe time.

Signed-off-by: Peter Ujfalusi <[email protected]>
(cherry picked from commit 69d56a7)
(cherry picked from commit 6571598)

Dynamic pipeline breaks mclk always-on feature by freeing dai
component in HW_FREE stage; the ssp_remove() will be called and
disables mclk unconditionally.

Signed-off-by: Brent Lu <[email protected]>
(cherry picked from commit 6dc474c)
(cherry picked from commit d5e3c70)